A subscriber line circuit with echo elimination is described in the article "Line Circuit Component SLAC for AXE 10" published in Ericsson Review, No. 4, 1983, pages 186-191. Included among other things in the receiving branch of the line circuit is a lowpass filter and a so-called interpolation filter in which the clock frequency, i.e. the sampling frequency, is increased. Included in the transmission branch, among other things, is a so-called decimation filter in which the clock frequency is reduced, and a bandpass filter having an upper limit frequency of 3.4 kHz. Echo elimination is effected with the aid of a digital filter, a so-called balance filter, in an interface between the input of the interpolation filter and the output of the decimation filter. The balance filter coefficients are determined, in a known manner, so that its transfer function, as far as possible, will equal the 25 transfer function of the echo path giving rise to the echo. Thus, the echo path includes the interpolation filter and the decimation filter, among others.
The information signals transmitted are originally sampled at a sampling frequency of 8 kHz. The clock frequency, however, is 16 kHz in the interface where the balance filter is connected, due to the fact that this frequency is increased upstream of the lowpass filter in the receiving branch and is decreased downstream of the bandpass filter in the transmission branch. It may appear disadvantageous to connect the balance filter at a point where the clock frequency is 16kHz instead of 8 kHz. A higher clock frequency namely requires a longer and more calculation-demanding filter than at a lower frequency, with the assumption that the filter impulse response shall have a given length. In itself, it is possible to connect the balance filter upstream of the lowpass filter in the receiving branch and downstream of the bandpass filter in the transmission branch in an interface where the clock frequency is 8 kHz. This would mean, however, that the lowpass filter and the bandpass filter, and also gain regulators and equalizing filters coupled in the receiving branch and in the transmission branch, would be included in the echo path. This would make it necessary to use a still longer balance filter than when the filter is coupled at a point where the clock frequency is 16 kHz.
Another example of a subscriber line circuit with echo elimination is known from the article "A 3-.mu.m CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting", published in IEEE Journal of Solid State Circuits, Vol. SC-20, No. 3, June 1985, pages 679-687. Transmitted signals are originally sampled at the frequency of 8 kHz. In this circuit, the clock frequency has been increased to 32 kHz in the interface where the balance filter is connected. A clock frequency of 16 kHz is used, however, for the filter. Because the clock frequency of the filter is 16kHz , it is possible to use a shorter and less calculating-demanding filter than when a clock frequency of 32 kHz has been used for the filter.